RapidSmith is a research-based, open source FPGA CAD tool written in Java for modern Xilinx FPGAs. Based on XDL, its objective is to serve as a rapid prototyping platform for research ideas and algorithms relating to low level FPGA CAD tools.
The development of RapidSmith was supported, in part, by the National Science Foundation Under Grant No. 0801876 as a part of the CHREC Center for High-Performance Reconfigurable Computing.
A paper describing RapidSmith was presented by Brent Nelson at FPL 2011 won the "Community Service Award" at the conference. The paper describes the major components and provides several examples of how to use RapidSmith.
Update RapidSmith to 0.5.1 with a number of bug fixes and added several new methods in the design package. The Instance, Module and Pin class have been updated to include better data structures to provide faster and more convenient access to its members. The routing infrastructure has partially been re-written. See Release Notes for more details. You can download it now or check it out using SVN.
RapidSmith and HMFlow (our rapid prototyping compilation flow built on RapidSmith) will be demonstrated at FCCM Demo Night this year. We have a paper on HMFlow which will be presented that same day. If you are going to FCCM, be sure to come visit us!
The new version 0.5.0 of RapidSmith now includes all the device files needed, no more lengthy install process! It also includes several other features such as Virtex 7 and Kintex7 support. The wire hash map used to store all wire connections has been custom written and now uses half as much heap space, loads device files upto twice as fast and also routes significantly faster in most cases. See Release Notes for more details. You can download it now or check it out using SVN.
Sourceforge is slow serving up our dynamic pages so I have switched to some static pages and added a new page called related sites. Related sites has most of the links that are relevant to RapidSmith including some up and coming open source FPGA CAD projects like Torc.
RapidSmith has another major update release, 0.4.0. This release contains a very exciting feature, bitstream parsing/manipulation/export for Virtex 4, Virtex 5 and Virtex 6 architectures. Several new packages have been added to enable this feature (although, it only parses at the packet and frame level, according to Xilinx documentation). This feature opens up several new possibilities for RapidSmith. It also has a new unified approach to the pin mapping problem (missing information in the XDLRC report) of primitive site pins. It has several bug fixes and new methods added. See Release Notes for more details. You can download it now or check it out using SVN.
RapidSmith has had a major update release to version 0.3.0. A major change was changing the device files version (requiring you to rebuild the device files). This was done to enable preliminary support of a lot of legacy devices from Xilinx (Spartan 2, Spartan 2E, Spartan 3, Spartan 3A, Spartan 3ADSP, Spartan 3E, Virtex, Virtex E, Virtex 2, and Virtex 2 Pro). An new experimental timing report parser (Xilinx Trace TWR report files) has been added. Several bug fixes and a new FamilyType to help users distinguish the Xilinx FPGA families is now integrated. Several bug when routing Virtex 5 designs have been fixed. See Release Notes for more details. You can download it now or check it out using SVN.
Check out the news page for older updates.
The best place to start is in our documentation which will help you get RapidSmith up and running on your machine.
Next, check out the examples provided in the examples package to start learning how to write your own FPGA CAD tools.
